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Product
E/W
Cycles
Density
(Organization)
Page Size
Write Speed
Max. Clock
Frequency
Operating Voltage
(V)
Temps
Unique Features
Packages (1)
SPI? Compatible Serial EEPROM Family – Page Write mode, HOLD pin, software enabled block write protection and hardware write-protect pin. Supports SPI? modes
0, 3. (continued)
25LC160A
25AA160A
25LC160B
25AA160B
25C320
25LC320
25AA320
25LC640
25AA640
25LC256
25AA256
1M
1M
1M
1M
100K
1M
1M
1M
1M
1M
1M
16 Kbits (x8)
16 Kbits (x8)
16 Kbits (x8)
16 Kbits (x8)
32 Kbits (x8)
32 Kbits (x8)
32 Kbits (x8)
64 Kbits (x8)
64 Kbits (x8)
256 Kbits (x8)
256 Kbits (x8)
16B
16B
32B
32B
32B
32B
32B
32B
32B
64B
64B
5 ms
5 ms
5 ms
5 ms
5 ms
5 ms
5 ms
5 ms
5 ms
5 ms
5 ms
10 MHz
10 MHz
10 MHz
10 MHz
3 MHz
2 MHz
1 MHz
3 MHz
1 MHz
10 MHz
10 MHz
2.5 to 5.5
1.8 to 5.5
2.5 to 5.5
1.8 to 5.5
4.5 to 5.5
2.5 to 5.5
1.8 to 5.5
2.5 to 5.5
1.8 to 5.5
2.5 to 5.5
1.8 to 5.5
I, E
I
I, E
I
I, E
I, E
I
I, E
I
I. E
I
P, SN, ST, MS
P, SN, ST, MS
P, SN, ST, MS
P, SN, ST, MS
P, SN
P, SN, X/ST
P, SN, X/ST
P, SN, X/ST
P, SN, X/ST
P, SN, ST, MF
P, SN, ST, MF
NOTE 1. X/ST package code denotes rotated pinout.
Product
E/W
Cycles
Density
(Organization)
Write Speed
Max. Clock
Frequency
Operating Voltage (V)
Temps
Unique Features
Packages
Identification Products (Application-Specific Products for Monitors, DRAM Modules, ACR Risers and Other Plug-And-Play Applications)
Completely implements DDC1?/DDC2? interface for VESA
24LC21
1M
1 Kbit (x8)
10 ms
400 kHz
2.5 to 5.5
C, I
monitor identification. Improved noise filter. Write protection
pin. Not recommended for new designs. Use 24LC21A or
P, SN
24LCS21A.
Same as 24LC21 plus software enabled write-protect pin. Not P, SN
24LCS21
1M
1 Kbit (x8)
10 ms
400 kHz
2.5 to 5.5
C, I
recommended for new designs. Use 24LC21A or 24LCS21A.
24LC21A
24LCS21A
1M
1M
1 Kbit (x8)
1 Kbit (x8)
10 ms
10 ms
400 kHz
400 kHz
2.5 to 5.5
2.5 to 5.5
C, I
C, I
Same features as 24LC21 plus “return to DDC1” feature.
Same features as 24LC21A plus software enabled write-
protect pin.
P, SN
P, SN
Implements VESA E-EDID 1.3 for flat panels and projectors.
24LCS22A
1M
2 Kbits (x8)
10 ms
400 kHz
2.5 to 5.5
I
Includes “return to DDC1” feature and software - enabled write P, SN
protect pin.
24LC024
24LC025
1M
1M
2 Kbits (x8)
2 Kbits (x8)
10 ms
10 ms
400 kHz
400 kHz
2.5 to 5.5
2.5 to 5.5
C, I
C, I
Addressable, hardware write protection for DRAM DIMM
modules and other applications.
Addressable. No write-protect.
P, SN, ST, MS
P, SN, ST, MS
Addressable, hardware write protection and software write
24AA52
1M
2 Kbits (x8)
10 ms
400 kHz
1.8 to 5.5
I
protection for lower half of the array. Designed for DRAM
P, SN, ST, MS
DIMM modules.
24LCS52
1M
2 Kbits (x8)
10 ms
400 kHz
2.5 to 5.5
I
P, SN, ST, MS
PAGE 65
Memory
Family Products
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